Note: The "Rss" resistor prevents shunting current directly from "A" and "B" to the output. Without it, if the circuit that provides inputs A and B does not have the proper driving capability, the output might not swing rail to rail or be severely slew-rate limited. The "Rss" resistor also limits the current from Vdd to ground which protects the transistors and saves energy when the transistors are transitioning between states.
For the NAND constructions, the upper arrangement requires fewer gates. For the NOR constructions, the lower arrangement offers the advantage of a shorter propagation delay (the time delay between an input changing and the output changing).
Literal interpretation of the name "exclusive or", or observation of the IEC rectangular symbol, raises the question of correct behaviour with additional inputs. If a logic gate were to accept three or more inputs and produce a true output if exactly one of those inputs were true, then it would in effect be a one-hot detector (and indeed this is the case for only two inputs). However, it is rarely implemented this way in practice.
1110100101 (data) 11010 (target) 00111 (XOR) 2 zero bits 1110100101 11010 00000 5 zero bits 1110100101 11010 01110 2 zero bits 1110100101 11010 10011 2 zero bits 1110100101 11010 01000 4 zero bits 1110100101 11010 11111 0 zero bits Matches by offset: . : : : : : : : ----------- 0 1 2 3 4 5
In this example, the best match occurs when the target sequence is offset by 1 bit and all five bits match. When offset by 5 bits, the sequence exactly matches its inverse. By looking at the difference between the number of ones and zeros that come out of the bank of XOR gates, it is easy to see where the sequence occurs and whether or not it is inverted. Longer sequences are easier to detect than short sequences.