Physical layer

In the seven-layer OSI model of computer networking, the physical layer or layer 1 is the first and lowest layer; The layer most closely associated with the physical connection between devices. This layer may be implemented by a PHY chip.

The physical layer defines the means of transmitting a stream of raw bits[1] over a physical data link connecting network nodes. The bitstream may be grouped into code words or symbols and converted to a physical signal that is transmitted over a transmission medium. The physical layer provides an electrical, mechanical, and procedural interface to the transmission medium. The shapes and properties of the electrical connectors, the frequencies to broadcast on, the line code to use and similar low-level parameters, are specified by the physical layer.

The physical layer consists of the electronic circuit transmission technologies of a network.[2] It is a fundamental layer underlying the higher level functions in a network, and can be implemented through a great number of different hardware technologies with widely varying characteristics.[3]

Within the semantics of the OSI model, the physical layer translates logical communications requests from the data link layer into hardware-specific operations to cause transmission or reception of electronic (or other) signals.[4][5] The physical layer supports higher layers responsible for generation of logical data packets.

In a network using Open Systems Interconnection (OSI) architecture, the physical signaling sublayer is the portion of the physical layer that[6][7]

The Internet protocol suite, as defined in and , is a high-level networking description used for the Internet and similar networks. It does not define a layer that deals exclusively with hardware-level specifications and interfaces, as this model does not concern itself directly with physical interfaces.[8][9]

The major functions and services performed by the physical layer are: The physical layer performs bit-by-bit or symbol-by-symbol data delivery over a physical transmission medium.[10] It provides a standardized interface to the transmission medium, including[11][12] a mechanical specification of electrical connectors and cables, for example maximum cable length, an electrical specification of transmission line signal level and impedance. The physical layer is responsible for electromagnetic compatibility including electromagnetic spectrum frequency allocation and specification of signal strength, analog bandwidth, etc. The transmission medium may be electrical or optical over optical fiber or a wireless communication link such as rree-space optical communication or radio.

Line coding is used to convert data into a pattern of electrical fluctuations which may be modulated onto a carrier wave or infrared light. The flow of data is managed with bit synchronization in synchronous serial communication or start-stop signalling and flow control in asynchronous serial communication. Sharing of the transmission medium among multiple network participants can be handled by simple circuit switching or multiplexing. More complex medium access control protocols for sharing the transmission medium may use carrier sense and collision detection such as in Ethernet's (CSMA/CD).

To optimize reliability and efficiency, signal processing techniques such as equalization, training sequences and pulse shaping may be used. Error correction codes and techniques including forward error correction[13] may be applied to further improve reliability.

Other topics associated with the physical layer include: bit rate; point-to-point, multipoint or point-to-multipoint line configuration; physical network topology, for example bus, ring, mesh or star network; serial or parallel communication; simplex, half duplex or full duplex transmission mode; and autonegotiation[14]

A PHY, an abbreviation for "physical layer", is an electronic circuit, usually implemented as an integrated circuit, required to implement functions of the OSI model in a network interface controller.

A PHY connects a link layer device (often called MAC as an acronym for medium access control) to a physical medium such as an optical fiber or copper cable. A PHY device typically includes both Physical Coding Sublayer (PCS) and Physical Medium Dependent (PMD) layer functionality.[15]

-PHY may also be used as a suffix to form a short name referencing a specific physical layer protocol, for example M-PHY.

Modular transceivers for fiber-optic communication (like the SFP family) complement a PHY chip and form the PMA sublayer.

Micrel KS8721CL - 3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver

The Ethernet PHY is a component that operates at the of the OSI network model. It implements the physical layer portion of the Ethernet. Its purpose is to provide analog signal physical access to the link. It is usually interfaced with a Media Independent Interface (MII) to a MAC chip in a microcontroller or another system that takes care of the higher layer functions.

More specifically, the Ethernet PHY is a chip that implements the hardware send and receive function of Ethernet frames; it interfaces between the analog domain of Ethernet's line modulation and the digital domain of link-layer packet signaling.[16] The PHY usually does not handle MAC addressing, as that is the link layer's job. Similarly, Wake-on-LAN and Boot ROM functionality is implemented in the network interface card (NIC), which may have PHY, MAC, and other functionality integrated into one chip or as separate chips.

Common ethernet interfaces include fiber, or two to four copper pairs for data communication. However, there now exists a new interface, called Single Pair Ethernet (SPE), which is able to utilize a single pair of copper wires while still communicating at the intended speeds. Texas Instruments DP83TD510E[17] is an example of a PHY which uses SPE.

Examples include the Microsemi SimpliPHY and SynchroPHY VSC82xx/84xx/85xx/86xx family, Marvell Alaska 88E1310/88E1310S/88E1318/88E1318S Gigabit Ethernet transceivers, Texas Instruments DP838xx family[18] and offerings from Intel[19] and ICS.[20]